Data transmission networks process different types of data utilizing different types of memory systems. For example, when managing collected data, e.g., data packets, some conventional systems store and manage data using single port monolithic memories. As a result, conventional systems process requests for memory requests in an inefficient manner due to processing limitations resulting from the use of single-port configurations.
For example, assume that a single ported monolithic memory is configured to process multiple data requests or transactions. The requests may be to read data from memory or to write new data to memory. Multiple requests often address the same memory for read or write operations at the same time. Thus, a decision is made regarding which requests will access the memory block first. As a result, large latency times may be incurred since each unprocessed stalled request must wait until the previous request(s) is processed. The resulting latency ensures that pipelined data or “ordered” data is retrieved from or written to memory to maintain data integrity.
Other conventional systems, in an attempt to eliminate or reduce latency resulting from adhering to a pipelined order for data elements, are configured to retrieve data “out of order” or in a non-pipelined manner. These conventional systems must subsequently process the retrieved data elements in the order in which they were intended to be written to or read from memory. However, these subsequent processing steps potentially result in a breach of data integrity since an “out of order” request may request data that was later replaced or updated by an earlier request or transaction. Additionally, in order to process the data retrieved in a non-pipelined manner, conventional systems may require additional hardware/software to place the retrieved data into the desired sequence. Thus, the latency time saved is negated by subsequent processing time, data integrity risks, and additional components.
Thus, some delay, whether from latency or subsequent processing, is inherent in conventional memory systems when attempting to process multiple, simultaneous data requests in a pipelined manner. As a result, given the potential hardware, networking, processing, and memory requirements, data read and write requests may require unnecessary clock cycles resulting in inefficient processing of requests to read data from memory or to write data to memory.
Thus, there is a need in the art for a data processing network that can interface with existing networks and systems with data, and process multiple, simultaneous data requests utilizing related memory in an time, cost, and space efficient manner.